1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a NAND flash memory device that includes a dummy cell.
This U.S. non-provisional patent application claims priority under 35 U.S.C § 119 to Korean Patent Application 2006-002310 filed on Jan. 09, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Generally, NAND flash memory devices are programmed and erased using Fowler-Nordheim (F-N) tunneling. In F-N tunneling, electrons are injected/discharged from/to a channel region into/from a floating gate due to a large voltage difference between the channel region and a control gate of a cell transistor. Because of the relative ease in programming and erasing NAND flash memory devices, NAND flash memory devices are known to have good data storage characteristics as compared to other non-volatile memory devices. Moreover, NAND flash memory devices are also capable of high density integration, low power dissipation, and durability of percussion. These and other such features have helped increase the usage of NAND flash memory devices in recent years.
For example, the NAND flash memory is increasingly considered as a substitute for hard disk driver (HDD) as an auxiliary memory unit that is known as a solid state disk (SSD). While a SSD is considered to be inferior in capacity and cost to the HDD, the SSD is considered to be superior in access speed, miniaturization, and durability of percussion to the HDD. Moreover, it is expected that the progress of design and process technologies may increase the capacity and decrease the cost of the SSD. For these reasons, the SDD may be increasingly used as an auxiliary memory unit instead of the HDD.
While an increase in the integration density of memory cells in a semiconductor device may help reduce the size of the device, an increase in integration density may also cause problems. For example, the more highly integrated the memory device is, the more closely the memory cells are formed. This reduction in space between the memory cells may lead to an increase in coupling between memory cells. Furthermore, as the integration degree of the flash memory device is increased, a string may include more memory cells. This increase in memory cells with less space between them may cause a charge sharing phenomenon that may reduce a boosted channel voltage (e.g., about 9V) to a lower channel voltage (e.g., about 6V). The lowering of the channel voltage may make program-inhibit cells programmed. This programming of program-inhibit cells is generally undesirable.
FIG. 1 shows a schematic circuit diagram of a string structure of a conventional flash memory device. Referring to FIG. 1, a string comprises a string selection transistor SST, a ground selection transistor GST, and 32 memory cells MC<0> through MC<31> connected in series between the string selection transistor SST and the ground selection transistor GST. A drain of the string selection transistor SST is connected to a bit line and a source of the ground selection transistor GST is connected to a common source line CSL. A control gate of the string selection transistor SST is connected to a string selection line SSL and a control gate of the ground selection transistor GST is connected to a ground selection line GSL.
For exemplary purposes, it is assumed that a memory cell 10 is to be programmed and an adjacent memory cell MC<30> to the memory cell 10 is to be program-inhibited. Furthermore, a self-boosting scheme is used to program-inhibit the adjacent memory cell MC<30>. According to the program-inhibit method using the self-boosting scheme, a ground voltage (e.g., 0V) is applied to the control gate of the ground selection transistor GST so as to block a ground path of a string. The ground voltage is also applied to a selected bit line BL<m> connected to a string that comprises the memory cell 10 to be programmed. In addition, a source voltage (e.g., Vcc) is applied to an unselected bit line BL<m+1> connected to a string that comprises the memory cell MC<30> to be program-inhibited. Simultaneously, the source voltage (Vcc) is applied to the string selection line SSL. According to this bias condition, a source of the string selection transistor SST that is connected to the unselected bit line BL<m+1> is charged up to a voltage of (Vcc-Vth) (Vth is a threshold voltage of the SST). At this time, the SST is shut off so that the string with the memory cell to be program-inhibited is electrically isolated from the unselected bit line BL<m+1>. That is, the channel with the memory cell to be program-inhibited is floated.
Under this condition, a program voltage Vpgm is applied to a selected word line WL<30> and a pass voltage Vpass is applied to each of unselected word lines WL<0> through WL<29> and WL<31>. As a result, the channel of the program-inhibit memory cell (MC<30>) is self-boosted due to the capacitive coupling between its gate and channel, with the channel being floated. Furthermore, the voltage difference between the gate and the channel is so small that the electrons do not tunnel to the floating gate, thereby preventing the program-inhibit memory cell (MC<30>) from being programmed.
While the above-mentioned self-boosting scheme may be used to program-inhibit a memory cell, this scheme may not work as well in a high integration density memory device. For example, as the number of memory cells in a string increases, the charge-sharing of the self-boosted channel of the program-inhibited memory cell MC<30> increases. This reduces the channel voltage in the program-inhibited memory cell MC<30>. The resulting channel voltage decrease increases the voltage difference between the gate and the channel. This increase in the potential difference between the gate and channel may lead to an undesirable programming operation.
A local self-boosting scheme may be used to solve the above-mentioned problem. As depicted in FIG. 1, arrows indicate a charge-sharing direction and a programming direction. According to the local self-boosting scheme, a ground voltage of 0V is applied to two unselected word lines disposed at both sides of a selected word line. Furthermore, a program voltage Vpgm is applied to the selected word line after the pass voltage Vpass (e.g., about 10V) is applied to the remaining unselected word lines. Under the bias condition, the channel of a program-inhibited memory cell is locally boosted and the inactivated channels of two memory cells adjacent to the program-inhibited memory cell enables charges in the locally boosted channel to be blocked. As a result, the channel voltage of the program-inhibited memory cell is preserved so that the F-N tunneling in the program-inhibited memory cell is prevented.
While the local self boosting scheme may be used to prevent F-N tunneling in the program-prohibited memory cell, the scheme has several drawbacks. For example, the higher integration of the flash memory may narrow the interval between word lines. The narrow interval between word lines may result in a large coupling ratio between a selected word line (being applied with Vpgm) and unselected word lines (being applied with 0V). In other words, the voltage of unselected word lines may increase because of the coupling with the selected word line. This means that the unselected memory cells supplied with 0V are turned on because of charge sharing. Thus, because of the relatively large coupling ratio between unselected world lines and a selected word line, it may be undesirable to apply the local self boosting scheme to a highly integrated flash memory.
FIG. 2 shows a cross-sectional view of a string in FIG. 1. Referring to FIG. 2, a source voltage Vcc is applied to a gate of a string selection transistor SST and a bit line BL<m+1>. In addition, a ground voltage of 0V is applied to a ground selection transistor GST. Furthermore, a program voltage Vpgm is applied to a gate of a cell transistor MC<30> which is a program-inhibited memory cell. A pass voltage Vpass is applied to the remaining unselected word lines, respectively. Under this bias condition, a channel voltage of the cell transistor MC<30> is self-boosted such that the channel charge density of the cell transistor MC<30> is much higher than that of respective unselected cell transistors. However, cell transistors MC<0>˜MC<29> are turned on because they are supplied with the pass voltage Vpass which is much higher than a threshold voltage. For this reason, the channels of the unselected cell transistors MC<0>˜MC<29> are formed. Especially, in a case where a cell transistor has a low threshold voltage (or an erased state), the size of the channel formed may be enlarged because of the pass voltage Vpass applied to the cell transistor. The capacitance formed by channels of the unselected cell transistors MC<0>˜MC<29> may share the boosted channel charge of the cell transistor MC<30>. This charge sharing causes a drop in the channel voltage of the cell transistor MC<30>. This drop in the channel voltage of the cell transistor MC<30> may lead to an undesirable programming operation due to increase in a voltage difference between the gate and the channel.
The above-mentioned drawback may become an important issue in a NAND flash memory device which starts a programming operation from a word line WL<0> in an ascending order. In other words, in a case where a selected word line is closer to the string selection transistor SST, the number of cell transistors which cause the charge sharing increase. This means that the total capacitance of channels increases as a selected word line becomes closer to the string selection transistor SST. Accordingly, as the channel capacitance of the unselected cell transistors increases, the charge shared amongst the cell transistor MC<30> and the unselected cell transistors increases, thus increasing the likelihood that the cell transistor MC<30> is programmed.
FIG. 3 shows a channel voltage drop caused by the charge sharing at a program-inhibited cell transistor. Referring to FIG. 3, the channel voltage of a memory cell MC<30> is set up to a voltage of Vcc-Vth when string and ground selection transistors SST and GST are biased to boost its channel. Furthermore, when the program voltage (Vpgm) is applied to the gate of the memory cell MC<30> at time t1, the channel of the program-inhibited memory cell MC<30> should be boosted up to Vch1 to inhibit F-N tunneling. However, the charge sharing causes the boosted channel voltage Vch1 (about 9V) to fall down to Vch2 (about 6V). This reduction in the voltage level of the channel in, the program-inhibited memory cell MC<30> due to charge sharing may cause the memory cell MC<30> to be programmed.
The present disclosure is directed towards overcoming one or more of the problems associates with conventional flash memory devices.